阳东育龙学校好不好:RGB RAW 格式转换为 YUV格式的VHDL程序

来源:百度文库 编辑:中财网 时间:2024/05/02 07:44:50


bayer是低端彩色cmos sensor 常用的一种颜色模式,
下面的源码是一个bayer filter,输入8位bayer 数据,输出24位rgb,已经在fpga里验证过。
--------------------------------------------------------------------------------
-- Author      : Yang Yuning
--
-- Create Date : 11/21/05
-- Module Name : bayer_filter
--
-- Description : Bayer filter, which converts input image data in bayer pattern format to rgb format.
--
--               color_sel    :       "00"            "01"            "10"            "11"
--               input stream :   BGBGBG....BG    GBGBGB....GB    GRGRGR....GR    RGRGRG....RG      
--                                        GRGRGR....GR    RGRGRG....RG    BGBGBG....BG    GBGBGB....GB
--                                        ............    ............    ............    ............
--                                        BGBGBG....BG    GBGBGB....GB    GRGRGR....GR    RGRGRG....RG
--                                       GRGRGR....GR    RGRGRG....RG    BGBGBG....BG    GBGBGB....GB
--
-- Copyright   : Institute of Computer Science V, University Mannheim, Germany
--------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bayer_filter is
       generic(
                   dw : integer := 8          
           );
           port(
                clk   : in std_logic;
            reset : in std_logic;

                        din_valid : in std_logic;
                        pixel_in  : in std_logic_vector(dw - 1 downto 0);
                        eof_in    : in std_logic;
                    eol_in    : in std_logic;
                        color_sel_in : in std_logic_vector(1 downto 0);
            
                        dout_valid  : out std_logic;
                        dout_r      : out std_logic_vector(dw - 1 downto 0);
                        dout_g      : out std_logic_vector(dw - 1 downto 0);
                        dout_b      : out std_logic_vector(dw - 1 downto 0);
                        eof_out     : out std_logic;
                        eol_out     : out std_logic
           );
end bayer_filter;

architecture rtl of bayer_filter is

-- pixel_window_3x3
component pixel_window_3x3 is
          generic(
                      dw : integer := 8               -- data width
              );
          port(
               clk   : in std_logic;
               reset : in std_logic;
                          
               din_valid : in std_logic;
                           pixel_in  : in std_logic_vector(dw - 1 downto 0);
                           eof_in    : in std_logic;
                           eol_in    : in std_logic;
                          
                           dout_valid : out std_logic;
                           w33        : out std_logic_vector(dw - 1 downto 0);
                           w32        : out std_logic_vector(dw - 1 downto 0);
                           w31        : out std_logic_vector(dw - 1 downto 0);
                           w23        : out std_logic_vector(dw - 1 downto 0);
                           w22        : out std_logic_vector(dw - 1 downto 0);
                           w21        : out std_logic_vector(dw - 1 downto 0);
                           w13        : out std_logic_vector(dw - 1 downto 0);
                           w12        : out std_logic_vector(dw - 1 downto 0);
                           w11        : out std_logic_vector(dw - 1 downto 0);
                           eof_out    : out std_logic;
                           eol_out    : out std_logic
              );
end component;

signal dvalid_pixel_window, dvalid_pixel_window_reg, eof_pixel_window, eof_pixel_window_reg, eol_pixel_window, eol_pixel_window_reg : std_logic := '0';
signal color_sel, color_sel_reg : std_logic_vector(1 downto 0) := (others => '0');

signal w33, w32, w31, w23, w22, w21, w13, w12, w11, w22_reg : std_logic_vector(dw - 1 downto 0) := (others => '0');

signal sum_w21w23 : std_logic_vector(dw downto 0):= (others => '0');
signal sum_w12w32 : std_logic_vector(dw downto 0):= (others => '0');
signal sum_w11w13 : std_logic_vector(dw downto 0):= (others => '0');
signal sum_w31w33 : std_logic_vector(dw downto 0):= (others => '0');

begin

-- pixel_window_3x3
inst_pixel_window : pixel_window_3x3
                    generic map (
                                     dw => dw
                        )
                    port map(
                             clk => clk, reset => reset,
                             din_valid => din_valid, pixel_in => pixel_in,
                                         eof_in => eof_in, eol_in => eol_in,

                                         dout_valid => dvalid_pixel_window,
                                         w33 => w33, w32 => w32, w31 => w31,
                                         w23 => w23, w22 => w22, w21 => w21,
                                         w13 => w13, w12 => w12, w11 => w11,
                                         eof_out => eof_pixel_window, eol_out => eol_pixel_window
                        );

-- control signal registers
process (clk)
begin
    if clk'event and clk = '1' then
            if reset = '1' or eof_pixel_window = '1' then
            color_sel <= color_sel_in;
            elsif eol_pixel_window = '1' then
                color_sel(1) <= not color_sel(1);
                color_sel(0) <= '0';
            elsif dvalid_pixel_window = '1' then
                color_sel(0) <= not color_sel(0);
            end if;
    end if;
end process;

-- color mixer
process(clk)
variable sum_w11w13w31w33, sum_w12w21w23w32 : std_logic_vector(dw + 1 downto 0);
begin
    if clk'event and clk = '1' then
            dvalid_pixel_window_reg <= dvalid_pixel_window;
               eof_pixel_window_reg <= eof_pixel_window;
                eol_pixel_window_reg <= eol_pixel_window;

                dout_valid <= dvalid_pixel_window_reg;
               eof_out <= eof_pixel_window_reg;
                eol_out <= eol_pixel_window_reg;
                
                color_sel_reg <= color_sel;
        
                -- color mixer
                if dvalid_pixel_window = '1' then
                    w22_reg <= w22;
                    sum_w21w23 <= ('0'&w21) + ('0'&w23);
                    sum_w12w32 <= ('0'&w12) + ('0'&w32);
                    sum_w11w13 <= ('0'&w11) + ('0'&w13);
                    sum_w31w33 <= ('0'&w31) + ('0'&w33);
                end if;
                
                sum_w12w21w23w32 := ('0'&sum_w12w32) + ('0'&sum_w21w23);
                sum_w11w13w31w33 := ('0'&sum_w11w13) + ('0'&sum_w31w33);
                
                case color_sel_reg is
            when "00"=>                                                      -- BGB
                    dout_r<= w22_reg;                                  -- GRG
                    dout_g<= sum_w12w21w23w32(dw + 1 downto 2);   -- BGB
                        dout_b<= sum_w11w13w31w33(dw + 1 downto 2);
                when "01"=>                                                      -- GBG
                    dout_r<= sum_w21w23(dw downto 1);             -- RGR
                    dout_g<= w22_reg;                             -- GBG
                    dout_b<= sum_w12w32(dw downto 1);          
                when "10"=>                                                      -- GRG
                    dout_r<= sum_w12w32(dw downto 1);                  -- BGB
                    dout_g<= w22_reg;                                   -- GRG
                    dout_b<= sum_w21w23(dw downto 1);          
                when "11"=>                                                      -- RGR
                    dout_r<= sum_w11w13w31w33(dw + 1 downto 2);   -- GBG
                    dout_g<= sum_w12w21w23w32(dw + 1 downto 2);   -- RGR
                    dout_b<= w22_reg;
                when others =>
                    dout_r <= (others => 'X');
                        dout_g <= (others => 'X');
                        dout_b <= (others => 'X');
            end case;
    end if;
end process;



end rtl;